1. Field of the Invention
The present invention relates to a variable capacitance circuit and an integrated circuit containing the variable capacitance circuit.
2. Description of the Related Art
A conventional technique of switching the gain of a voltage amplifier circuit by switching an input capacitance is known in Japanese Laid Open Patent Application (JP-P2003-17959A). FIG. 1 shows such a variable gain amplifier.
The variable gain amplifier shown in FIG. 1, is composed of a coupling capacitor 10, a pair of switches 92 and 94, capacitors 91 and 93, and inverters 321 and 323. The coupling capacitor 10 is connected to an input terminal Ti at one terminal. Each of the switches 92 and 94 (N-MOS transistors) has a first contact (source or drain) connected to the other end of the coupling capacitor 10. The capacitors 91 and 93 are respectively inserted between second contacts of the switches 92 and 94 and a ground conductor. The inverters 321 and 323 are connected in series. An amplifier circuit 940 has an input terminal connected to an input node 950 to which first contacts of the switches 92 and 94 are connected. The input terminal of the amplifier circuit 940 is the gate of an N-MOS transistor 943, and the drain of the N-MOS transistor 943 is connected to an output terminal To. A gain switch signal is supplied to an input terminal of the inverter 321. Output terminals of the inverters 321 and 323 are respectively are connected to control terminals (gates) of the switches 92 and 94.
In this conventional circuit, by switching the gain switch signal, one of the capacitors 91 and 93 can be connected to the node 950. In this conventional circuit, an approximate voltage amplification gain β in the path from the input terminal Ti to the output terminal To is represented by the following equation (1):β=α*C1*C1*(C2+Cdg+Csg)/(C2+α*Cdg+Csg)  (1)where α represents a gain of the amplifying N-MOS transistor 943, C2 is a capacitance between the node 950 and the ground conductor (in this case, the capacitance of one of the capacitors 91 and 93 which is connected to the node 950); Csg and Cdg represent a source-gate parasitic capacitance of the amplifying N-MOS transistor 943, and the drain-gate parasitic capacitance of the transistor 943, respectively.
Accordingly, as the capacitance C2 between the node 950 and the ground conductor increases, the amplification gain β reduces in an inverse proportional relation. As a result, the gain β of the amplifier circuit can be varied by changing the capacitance C2.
According to the above-described method, however, one capacitor should be provided to each of selectable gain values. Therefore, to realize a large number of gain values, the layout area for the capacitors on an IC chip increases proportionally to the increase in the number of capacitors.
In conjunction with the above description, a gain variable amplification device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-27722). In this conventional example, a first capacitor for negative feedback and a first switch for the gain switching are connected between an inversion input terminal and a positive side output terminal, a second capacitor is connected between the inversion input terminal and a fixed potential. A differential amplifier applies an input voltage to a non-inversion input terminal, and a second switch for gain switching is connected between the inversion input terminal and an output terminal A third capacitor is connected between the inversion input terminal and the fixed potential. An operational amplifier receives the positive side output of the differential amplifier at the non-inversion input terminal. A fourth capacitor for the negative feedback is connected between the inversion input terminal of the differential amplifier and which and the output terminal of the operational amplifier.
Also, a gain variable inversion amplifier circuit is disclosed in Japanese Laid Open Patent Application (JP-P2000-138548A). This conventional example includes one or more input capacitances to whose input an analog input voltage is connected. An input refreshment switch is connected with the input of the input capacitance and connects the analog input voltage or a reference voltage with the input capacitance. An amplifier is connected with the output of the input capacitance and generates an inversion output. One or more feedback capacitances are connected with the output of the amplifier. An amplifier refreshment switch connects the input and output of the amplifier. An output refreshment switch is connected with the output of the feedback capacitance and connects these outputs with the output of the amplifier or the reference voltage. A part of the input capacitance or feedback capacitance is invalidated to control the gain of the output voltage of the amplifier. One end of each of the input capacitances or feedback capacitances is connected with the amplifier input or the reference voltage by a multiplexer.
Also, a gain switching amplification circuit is disclosed in Japanese Laid Open Patent Application (JP-P2002-185274A). In this conventional example, emitters of first and second transistors are connected with a collector of a third transistor, which has a base connected an input, and an emitter connected with a second resistance and a first capacitor. A first resistance is connected between the input and a second power supply. The second power supply is connected between the first resistance and the ground. The second resistance is connected between the emitter of the third transistor and the ground. A first capacitor is connected between the emitter of the third transistor and the ground. The first transistor has a gate connected with a gain setting input, an emitter connected with the collector of the third transistor and a collector connected with the first power supply. The second transistor has a base connected with a fourth power supply, an emitter connected with the collector of the third transistor and a collector connected with the output. The first power supply is connected with the collector of the first transistor and a first inductor in one end and grounded at the other end. The first inductor is connected between the first power supply and the output. A fourth power supply is connected between the base of the second transistor and the ground. A second capacitor is connected between the input and the base of a fifth transistor. A third resistance is connected with the base of the second capacitor and the fifth transistor at one end and connected with the third power supply at the other end. The third power supply is connected between the third resistance and the ground. The fifth transistor has a base connected with the third resistance and the second capacitor, an emitter connected with the fourth resistance and the third capacitor and a collector connected with the emitter of the fourth transistor. A fourth resistance is connected with the emitter of the fifth transistor and the third capacitor at one end and grounded at the other end. The third capacitor is connected with the emitter of the fifth transistor and the fourth resistance at one end and grounded the other end. The fourth transistor has a base connected with the fourth power supply and the base of the second transistor, an emitter connected with the collector of the fifth transistor and a collector connected with the output.